// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
// Date        : Tue Nov 26 09:13:20 2019
// Host        : ubuntu running 64-bit Ubuntu 18.04.3 LTS
// Command     : write_verilog -mode funcsim -nolib -force -file
//               /home/cyx/Desktop/WEEK12-EDA-Laboratory-of-Electronic-Circuits/Module_1/M1.sim/sim_1/impl/func/xsim/counter_60_tb_func_impl.v
// Design      : counter_60_24
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* ECO_CHECKSUM = "a1fa6ed8" *) (* max_num = "60" *) 
(* NotValidForBitStream *)
module counter_60_24
   (clk_in,
    CLR,
    tns,
    uts,
    CO);
  input clk_in;
  input CLR;
  output [3:0]tns;
  output [3:0]uts;
  output CO;

  wire CLR;
  wire CLR_IBUF;
  wire CO;
  wire clk_in;
  wire clk_in_IBUF;
  wire clk_in_IBUF_BUFG;
  wire [5:1]num;
  wire \num_reg[0]_LDC_i_1_n_0 ;
  wire \num_reg[0]_LDC_i_2_n_0 ;
  wire \num_reg[0]_LDC_n_0 ;
  wire \num_reg[0]_P_n_0 ;
  wire \num_reg[1]_LDC_i_1_n_0 ;
  wire \num_reg[1]_LDC_i_2_n_0 ;
  wire \num_reg[1]_LDC_n_0 ;
  wire \num_reg[1]_P_n_0 ;
  wire \num_reg[2]_LDC_i_1_n_0 ;
  wire \num_reg[2]_LDC_i_2_n_0 ;
  wire \num_reg[2]_LDC_n_0 ;
  wire \num_reg[2]_P_n_0 ;
  wire \num_reg[3]_LDC_i_1_n_0 ;
  wire \num_reg[3]_LDC_i_2_n_0 ;
  wire \num_reg[3]_LDC_i_3_n_0 ;
  wire \num_reg[3]_LDC_n_0 ;
  wire \num_reg[3]_P_n_0 ;
  wire \num_reg[4]_LDC_i_1_n_0 ;
  wire \num_reg[4]_LDC_i_2_n_0 ;
  wire \num_reg[4]_LDC_n_0 ;
  wire \num_reg[4]_P_n_0 ;
  wire \num_reg[5]_LDC_i_1_n_0 ;
  wire \num_reg[5]_LDC_i_2_n_0 ;
  wire \num_reg[5]_LDC_i_3_n_0 ;
  wire \num_reg[5]_LDC_n_0 ;
  wire \num_reg[5]_P_n_0 ;
  wire [3:0]tns;
  wire [2:0]tns_OBUF;
  wire [3:0]uts;
  wire [3:0]uts_OBUF;

  IBUF CLR_IBUF_inst
       (.I(CLR),
        .O(CLR_IBUF));
  OBUF CO_OBUF_inst
       (.I(1'b0),
        .O(CO));
  BUFG clk_in_IBUF_BUFG_inst
       (.I(clk_in_IBUF),
        .O(clk_in_IBUF_BUFG));
  IBUF clk_in_IBUF_inst
       (.I(clk_in),
        .O(clk_in_IBUF));
  (* XILINX_LEGACY_PRIM = "LDC" *) 
  LDCE #(
    .INIT(1'b0)) 
    \num_reg[0]_LDC 
       (.CLR(\num_reg[0]_LDC_i_2_n_0 ),
        .D(1'b1),
        .G(\num_reg[0]_LDC_i_1_n_0 ),
        .GE(1'b1),
        .Q(\num_reg[0]_LDC_n_0 ));
  LUT3 #(
    .INIT(8'h07)) 
    \num_reg[0]_LDC_i_1 
       (.I0(\num_reg[0]_LDC_n_0 ),
        .I1(\num_reg[0]_P_n_0 ),
        .I2(CLR_IBUF),
        .O(\num_reg[0]_LDC_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \num_reg[0]_LDC_i_2 
       (.I0(\num_reg[0]_LDC_n_0 ),
        .I1(\num_reg[0]_P_n_0 ),
        .I2(CLR_IBUF),
        .O(\num_reg[0]_LDC_i_2_n_0 ));
  FDPE #(
    .INIT(1'b1)) 
    \num_reg[0]_P 
       (.C(clk_in_IBUF_BUFG),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\num_reg[0]_LDC_i_1_n_0 ),
        .Q(\num_reg[0]_P_n_0 ));
  (* XILINX_LEGACY_PRIM = "LDC" *) 
  LDCE #(
    .INIT(1'b0)) 
    \num_reg[1]_LDC 
       (.CLR(\num_reg[1]_LDC_i_2_n_0 ),
        .D(1'b1),
        .G(\num_reg[1]_LDC_i_1_n_0 ),
        .GE(1'b1),
        .Q(\num_reg[1]_LDC_n_0 ));
  LUT5 #(
    .INIT(32'h15404040)) 
    \num_reg[1]_LDC_i_1 
       (.I0(CLR_IBUF),
        .I1(\num_reg[1]_LDC_n_0 ),
        .I2(\num_reg[1]_P_n_0 ),
        .I3(\num_reg[0]_LDC_n_0 ),
        .I4(\num_reg[0]_P_n_0 ),
        .O(\num_reg[1]_LDC_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00008777)) 
    \num_reg[1]_LDC_i_2 
       (.I0(\num_reg[1]_LDC_n_0 ),
        .I1(\num_reg[1]_P_n_0 ),
        .I2(\num_reg[0]_LDC_n_0 ),
        .I3(\num_reg[0]_P_n_0 ),
        .I4(CLR_IBUF),
        .O(\num_reg[1]_LDC_i_2_n_0 ));
  FDPE #(
    .INIT(1'b1)) 
    \num_reg[1]_P 
       (.C(clk_in_IBUF_BUFG),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\num_reg[1]_LDC_i_1_n_0 ),
        .Q(\num_reg[1]_P_n_0 ));
  (* XILINX_LEGACY_PRIM = "LDC" *) 
  LDCE #(
    .INIT(1'b0)) 
    \num_reg[2]_LDC 
       (.CLR(\num_reg[2]_LDC_i_2_n_0 ),
        .D(1'b1),
        .G(\num_reg[2]_LDC_i_1_n_0 ),
        .GE(1'b1),
        .Q(\num_reg[2]_LDC_n_0 ));
  LUT6 #(
    .INIT(64'h0000000089999999)) 
    \num_reg[2]_LDC_i_1 
       (.I0(\num_reg[5]_LDC_i_3_n_0 ),
        .I1(num[2]),
        .I2(num[4]),
        .I3(num[3]),
        .I4(num[5]),
        .I5(CLR_IBUF),
        .O(\num_reg[2]_LDC_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0055551055105510)) 
    \num_reg[2]_LDC_i_2 
       (.I0(CLR_IBUF),
        .I1(\num_reg[3]_LDC_i_3_n_0 ),
        .I2(num[3]),
        .I3(\num_reg[5]_LDC_i_3_n_0 ),
        .I4(\num_reg[2]_P_n_0 ),
        .I5(\num_reg[2]_LDC_n_0 ),
        .O(\num_reg[2]_LDC_i_2_n_0 ));
  FDPE #(
    .INIT(1'b1)) 
    \num_reg[2]_P 
       (.C(clk_in_IBUF_BUFG),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\num_reg[2]_LDC_i_1_n_0 ),
        .Q(\num_reg[2]_P_n_0 ));
  (* XILINX_LEGACY_PRIM = "LDC" *) 
  LDCE #(
    .INIT(1'b0)) 
    \num_reg[3]_LDC 
       (.CLR(\num_reg[3]_LDC_i_2_n_0 ),
        .D(1'b1),
        .G(\num_reg[3]_LDC_i_1_n_0 ),
        .GE(1'b1),
        .Q(\num_reg[3]_LDC_n_0 ));
  LUT6 #(
    .INIT(64'h00000000C2D2D2D2)) 
    \num_reg[3]_LDC_i_1 
       (.I0(num[2]),
        .I1(\num_reg[5]_LDC_i_3_n_0 ),
        .I2(num[3]),
        .I3(num[5]),
        .I4(num[4]),
        .I5(CLR_IBUF),
        .O(\num_reg[3]_LDC_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1000233311112333)) 
    \num_reg[3]_LDC_i_2 
       (.I0(\num_reg[5]_LDC_i_3_n_0 ),
        .I1(CLR_IBUF),
        .I2(\num_reg[2]_LDC_n_0 ),
        .I3(\num_reg[2]_P_n_0 ),
        .I4(num[3]),
        .I5(\num_reg[3]_LDC_i_3_n_0 ),
        .O(\num_reg[3]_LDC_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \num_reg[3]_LDC_i_3 
       (.I0(\num_reg[4]_P_n_0 ),
        .I1(\num_reg[4]_LDC_n_0 ),
        .I2(\num_reg[5]_P_n_0 ),
        .I3(\num_reg[5]_LDC_n_0 ),
        .O(\num_reg[3]_LDC_i_3_n_0 ));
  FDPE #(
    .INIT(1'b1)) 
    \num_reg[3]_P 
       (.C(clk_in_IBUF_BUFG),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\num_reg[3]_LDC_i_1_n_0 ),
        .Q(\num_reg[3]_P_n_0 ));
  (* XILINX_LEGACY_PRIM = "LDC" *) 
  LDCE #(
    .INIT(1'b0)) 
    \num_reg[4]_LDC 
       (.CLR(\num_reg[4]_LDC_i_2_n_0 ),
        .D(1'b1),
        .G(\num_reg[4]_LDC_i_1_n_0 ),
        .GE(1'b1),
        .Q(\num_reg[4]_LDC_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AF40BF40)) 
    \num_reg[4]_LDC_i_1 
       (.I0(\num_reg[5]_LDC_i_3_n_0 ),
        .I1(num[2]),
        .I2(num[3]),
        .I3(num[4]),
        .I4(num[5]),
        .I5(CLR_IBUF),
        .O(\num_reg[4]_LDC_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h040B040F040B000F)) 
    \num_reg[4]_LDC_i_2 
       (.I0(\num_reg[5]_LDC_i_3_n_0 ),
        .I1(num[3]),
        .I2(CLR_IBUF),
        .I3(num[4]),
        .I4(num[2]),
        .I5(num[5]),
        .O(\num_reg[4]_LDC_i_2_n_0 ));
  FDPE #(
    .INIT(1'b1)) 
    \num_reg[4]_P 
       (.C(clk_in_IBUF_BUFG),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\num_reg[4]_LDC_i_1_n_0 ),
        .Q(\num_reg[4]_P_n_0 ));
  (* XILINX_LEGACY_PRIM = "LDC" *) 
  LDCE #(
    .INIT(1'b0)) 
    \num_reg[5]_LDC 
       (.CLR(\num_reg[5]_LDC_i_2_n_0 ),
        .D(1'b1),
        .G(\num_reg[5]_LDC_i_1_n_0 ),
        .GE(1'b1),
        .Q(\num_reg[5]_LDC_n_0 ));
  LUT6 #(
    .INIT(64'h4140444444444444)) 
    \num_reg[5]_LDC_i_1 
       (.I0(CLR_IBUF),
        .I1(num[5]),
        .I2(\num_reg[5]_LDC_i_3_n_0 ),
        .I3(num[2]),
        .I4(num[3]),
        .I5(num[4]),
        .O(\num_reg[5]_LDC_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000404055551555)) 
    \num_reg[5]_LDC_i_2 
       (.I0(CLR_IBUF),
        .I1(num[4]),
        .I2(num[3]),
        .I3(num[2]),
        .I4(\num_reg[5]_LDC_i_3_n_0 ),
        .I5(num[5]),
        .O(\num_reg[5]_LDC_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \num_reg[5]_LDC_i_3 
       (.I0(\num_reg[0]_P_n_0 ),
        .I1(\num_reg[0]_LDC_n_0 ),
        .I2(\num_reg[1]_P_n_0 ),
        .I3(\num_reg[1]_LDC_n_0 ),
        .O(\num_reg[5]_LDC_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \num_reg[5]_LDC_i_4 
       (.I0(\num_reg[2]_LDC_n_0 ),
        .I1(\num_reg[2]_P_n_0 ),
        .O(num[2]));
  FDPE #(
    .INIT(1'b1)) 
    \num_reg[5]_P 
       (.C(clk_in_IBUF_BUFG),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\num_reg[5]_LDC_i_1_n_0 ),
        .Q(\num_reg[5]_P_n_0 ));
  OBUF \tns_OBUF[0]_inst 
       (.I(tns_OBUF[0]),
        .O(tns[0]));
  LUT6 #(
    .INIT(64'h70FF8F70708F0870)) 
    \tns_OBUF[0]_inst_i_1 
       (.I0(\num_reg[2]_P_n_0 ),
        .I1(\num_reg[2]_LDC_n_0 ),
        .I2(num[4]),
        .I3(num[3]),
        .I4(num[5]),
        .I5(num[1]),
        .O(tns_OBUF[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \tns_OBUF[0]_inst_i_2 
       (.I0(\num_reg[3]_LDC_n_0 ),
        .I1(\num_reg[3]_P_n_0 ),
        .O(num[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \tns_OBUF[0]_inst_i_3 
       (.I0(\num_reg[1]_LDC_n_0 ),
        .I1(\num_reg[1]_P_n_0 ),
        .O(num[1]));
  OBUF \tns_OBUF[1]_inst 
       (.I(tns_OBUF[1]),
        .O(tns[1]));
  LUT6 #(
    .INIT(64'h800F0F0FF0808080)) 
    \tns_OBUF[1]_inst_i_1 
       (.I0(\num_reg[2]_LDC_n_0 ),
        .I1(\num_reg[2]_P_n_0 ),
        .I2(num[4]),
        .I3(\num_reg[3]_P_n_0 ),
        .I4(\num_reg[3]_LDC_n_0 ),
        .I5(num[5]),
        .O(tns_OBUF[1]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tns_OBUF[1]_inst_i_2 
       (.I0(\num_reg[4]_LDC_n_0 ),
        .I1(\num_reg[4]_P_n_0 ),
        .O(num[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \tns_OBUF[1]_inst_i_3 
       (.I0(\num_reg[5]_LDC_n_0 ),
        .I1(\num_reg[5]_P_n_0 ),
        .O(num[5]));
  OBUF \tns_OBUF[2]_inst 
       (.I(tns_OBUF[2]),
        .O(tns[2]));
  LUT6 #(
    .INIT(64'hF000800080008000)) 
    \tns_OBUF[2]_inst_i_1 
       (.I0(\num_reg[3]_LDC_n_0 ),
        .I1(\num_reg[3]_P_n_0 ),
        .I2(\num_reg[5]_LDC_n_0 ),
        .I3(\num_reg[5]_P_n_0 ),
        .I4(\num_reg[4]_LDC_n_0 ),
        .I5(\num_reg[4]_P_n_0 ),
        .O(tns_OBUF[2]));
  OBUF \tns_OBUF[3]_inst 
       (.I(1'b0),
        .O(tns[3]));
  OBUF \uts_OBUF[0]_inst 
       (.I(uts_OBUF[0]),
        .O(uts[0]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \uts_OBUF[0]_inst_i_1 
       (.I0(\num_reg[0]_LDC_n_0 ),
        .I1(\num_reg[0]_P_n_0 ),
        .O(uts_OBUF[0]));
  OBUF \uts_OBUF[1]_inst 
       (.I(uts_OBUF[1]),
        .O(uts[1]));
  LUT6 #(
    .INIT(64'h95AA40552A4095AA)) 
    \uts_OBUF[1]_inst_i_1 
       (.I0(num[1]),
        .I1(\num_reg[2]_P_n_0 ),
        .I2(\num_reg[2]_LDC_n_0 ),
        .I3(num[4]),
        .I4(num[3]),
        .I5(num[5]),
        .O(uts_OBUF[1]));
  OBUF \uts_OBUF[2]_inst 
       (.I(uts_OBUF[2]),
        .O(uts[2]));
  LUT6 #(
    .INIT(64'h40BD2B402B402B40)) 
    \uts_OBUF[2]_inst_i_1 
       (.I0(num[3]),
        .I1(num[5]),
        .I2(num[1]),
        .I3(num[4]),
        .I4(\num_reg[2]_LDC_n_0 ),
        .I5(\num_reg[2]_P_n_0 ),
        .O(uts_OBUF[2]));
  OBUF \uts_OBUF[3]_inst 
       (.I(uts_OBUF[3]),
        .O(uts[3]));
  LUT6 #(
    .INIT(64'h0888411124440888)) 
    \uts_OBUF[3]_inst_i_1 
       (.I0(num[1]),
        .I1(num[4]),
        .I2(\num_reg[2]_P_n_0 ),
        .I3(\num_reg[2]_LDC_n_0 ),
        .I4(num[5]),
        .I5(num[3]),
        .O(uts_OBUF[3]));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
